Power MOS transistors, also called DMOS transistors, are commonly used to drive inductive loads such as solenoids or DC motors. A DMOS transistor can transfer peak currents of up to 280 amps or continuous currents of up to 70 amps to an inductive load. The DMOS transistor may operate at voltages as high as 1,000 volts with a resistance as low as 0.02 ohms. The DMOS transistor is also not susceptible to thermal runaway or secondary breakdown problems.
DMOS transistors are typically fabricated in an IC chip which is connected to control the inductive load. The semiconductor structure of the DMOS transistor gives rise to parasitic effects which, under the appropriate conditions, may degrade the performance of the transistor. Specifically, body diodes, parasitic bipolar junction transistors (BJTs) and capacitances influence the operation of the DMOS transistor.
The parasitic effects may be illustrated with reference to a conventional H-bridge circuit shown in FIG. 1. An inductive load L is powered by four N-channel DMOS transistors, M1, M2, M3, and M4. A drain of the transistor M2 and a drain of the transistor M3 are connected to a voltage source Vcc. A source of the transistor M4 and a source of the transistor M1 are connected to a ground voltage reference. A source of the transistor M2 and a drain of the transistor M4 are connected to a first end of the inductive load L, and a source of the transistor M3 and a drain of the transistor M1 are connected to a second end of the inductive load L. Each of the DMOS transistors is shown with a respective body diode Db1, Db2, Db3, and Db4 connected between the source and the drain. The body diode is intrinsic to the structure of the DMOS transistor. Parasitic transistors QP and QP2 are also shown.
The four DMOS transistors of the H-bridge circuit control the delivery of current to the inductive load L. The DMOS transistors are alternately switched on and off to permit current to flow from the voltage source Vcc to the ground voltage reference. For example, when the transistors M1 and M2 are switched on and the transistors M3 and M4 are switched off, current will flow from the voltage source Vcc, through the transistor M2, the inductive load L, and the transistor M1 to the ground voltage reference. If the transistors M3 and M4 are switched on, and the transistors M1 and M2 are switched off, current will flow from the voltage source Vcc through the transistor M3, the inductive load L, and the transistor M4 to the ground voltage reference.
When the DMOS transistors switch on or off to change the direction of current in the inductive load L, the inductive load L will react by applying a transient voltage to oppose the changing current. The transient voltage will often activate the parasitic devices in the DMOS transistor. For example, with reference to FIG. 1, if the transistors M3 and M4 are conducting current through the inductive load L and are switched off, the inductive load L will react to maintain the current. Specifically, the drain of the transistor M1 will be driven below the ground voltage reference to draw current through the transistor M1, and the source of the transistor M2 will be driven above the voltage source Vcc to force current through the transistor M2. The parasitic effects may be demonstrated by examining the structure of the DMOS transistor.
A cross-sectional view of a conventional N-channel DMOS transistor 8 of the type used for the transistors M1-M4 is shown in FIG. 2. It has gate G, source S, and drain D, terminals as shown as well as a parasitic PNP transistor QP2 and a body diode Db. The structure of DMOS transistor 8 may be provided by a method known to those skilled in the art.
The body diode Db is comprised of a P.sup.+ type body region 10 and an N type epi pocket 12. The body diode Db is intrinsic to the structure of the DMOS transistor 8 and has a turn-on threshold voltage and a series resistance. The parasitic PNP transistor QP2 is comprised of the P.sup.+ body region 10 acting as an emitter, an N.sup.+ type drain region 14 and the epi pocket 12 acting as a base, and a P.sup.- type substrate 16 acting as a collector. A finite resistance in the P.sup.- substrate 16 is represented by a resistor Rsub. A P.sup.+ type region 18 links the P.sup.- substrate 16 with a ground voltage reference at a surface of the P.sup.- substrate 16. A second N type epi pocket 20 is shown in the P.sup.- substrate 16 to support a separate device.
The known DMOS transistor 8 operates as follows. When a voltage at the drain terminal D exceeds a voltage at the source terminal S, and a positive voltage is applied to the gate terminal G which exceeds a threshold voltage of the DMOS transistor 8, current flows from the drain terminal D and the N.sup.+ drain region 14 to two N.sup.+ type source regions 22 and 24 through N type channels induced in the P.sup.+ body region 10. When the voltage applied to the gate terminal G falls below the threshold voltage, the transistor is turned off and current through the DMOS transistor 8 stops.
The body diode Db and the parasitic PNP transistor QP2 may be activated when a voltage applied to the source terminal S of the DMOS transistor 8 exceeds a voltage at the drain terminal D of the DMOS transistor 8. This is called an oversupply effect. If the voltage at the source is sufficiently high, the body diode Db will be forward biased, and a recirculation current will flow from the source terminal S, through the P.sup.+ body region 10, the epi pocket 12, and the N.sup.+ drain region 14 to the drain terminal D. When the parasitic PNP transistor QP2 is activated, a portion of the current from the source terminal S will flow through the emitter, the base, and into the P.sup.- substrate 16 acting as the collector of the transistor QP2.
The efficiency of the transistor QP2 may be reduced by surrounding the DMOS transistor 8 with an N.sup.+ type region which, together with a buried N.sup.+ type layer, will act as a highly doped base so that only a small fraction of the current from the source terminal S (usually 3 to 4%) may reach the P.sup.- substrate 16. The current into the P.sup.- substrate 16 raises the potential of the substrate because it has a finite resistance Rsub. The epi pockets 12 and 20 have a voltage close to the voltage of the P.sup.- substrate 16 which enhances the effect of this current. A rising potential in the P.sup.- substrate 16 may forward bias junctions between the P.sup.- substrate 16 and the epi pockets 12 and 20, and consequently inject current into the epi pockets 12 and 20. Such current injection is highly undesirable. A conventional method of alleviating the effect is to connect the P.sup.- substrate 16 to a ground reference potential. However, this solution exacerbates another parasitic effect known as the below ground effect.
The below ground effect is described with reference to a cross-sectional view of the conventional N-channel DMOS transistor 8 shown in FIG. 3. The structure of the DMOS transistor 8 is identical to that of the DMOS transistor 8 shown in FIG. 2, and equivalent regions and elements have been given the same reference numerals. In addition to the regions and elements shown in FIG. 2, two N type epi pockets 26 and 28 support other devices located near the DMOS transistor 8 in the P.sup.- substrate 16. Each of the epi pockets 20, 26, and 28 receive a device current IcP. A parasitic, bulk distributed NPN transistor QP is shown having the epi pocket 12 and the N.sup.+ drain region 14 acting as an emitter, the P.sup.- substrate 16 and the P.sup.+ region 18 acting as a base, and each of the epi pockets 20, 26, and 28 acting as collectors for the transistor QP.
When the source terminal S of the DMOS transistor 8 is connected to the ground voltage reference and a voltage is applied to the drain terminal D sufficiently below the ground voltage reference, the below ground effect occurs. First, the body diode Db becomes forward biased and allows a recirculation current to pass from the source terminal S and the P.sup.+ body region 10 to the N.sup.+ drain region 14 and the drain terminal D. Second, the transistor QP is activated. The base emitter junction of the transistor QP will become forward biased in this instance because the base of the transistor QP is held to the ground voltage reference while the voltage at the emitter is driven below the ground voltage reference. Each of the epi pockets 20, 26, and 28 may deliver some current as collectors to the transistor QP. The recirculation current drawn by the source terminal S of the DMOS transistor 8 is split between the body diode Db and the transistor QP. Typically, the emitter of the transistor QP carries between 10% and 50% of the recirculation current, depending on the relevant efficiencies of the body diode Db and the forward biased base emitter junction of the transistor QP. The split of the recirculation current may be worse if a sense resistor is connected in series with the DMOS transistor 8. In fact, a voltage drop across the sense resistor may make the junction between the P.sup.+ body region 10 and the N.sup.+ drain region 14 inefficient with the result that all of the recirculation current may be injected into the P.sup.- substrate 16.
If the DMOS transistor 8 is subject to either the oversupply effect or the below ground effect, and sufficient current is drawn through one of the parasitic transistors QP2 or QP, an avalanche breakdown or a secondary breakdown of the respective parasitic transistor may occur which could result in a catastrophic failure of the DMOS transistor 8. When current is drawn through one of the parasitic transistors into the P.sup.- substrate 16, and the voltage of the P.sup.- substrate 16 is raised due to its resistance Rsub, then there is the potential of a turn-on of an SCR which may lead to a latch condition, which is very dangerous.
Several techniques have been implemented to overcome the effects of the body diode and parasitic bipolar devices within the DMOS structure. In one approach, an external silicon diode is placed in parallel with the DMOS structure, and a low voltage Schottky diode is placed in series with the drain of DMOS structure. The external silicon diode diverts current away from the body diode and the parasitic bipolar devices. However, with this approach, the DMOS structure sacrifices power to the Schottky diode and the external diodes increase the cost of the device. Another method includes completely isolating the device with a well region. Although this method may be fairly effective, it is very expensive and presents the risk of parasitic SCR. A third approach involves a technique for modifying the body diode so that the minority carriers in the P and N regions have a shorter lifetime which decreases the recombination time. However, this modification increases the resistance of the P and N type materials and complicates the fabrication of the DMOS structure.
A fourth method for preventing parasitic effects in an N-channel DMOS transistor is described in U.S. Pat. No. 4,811,065 to Cogan which is incorporated herein by way of reference. Cogan discloses a conventional vertical DMOS transistor having a Schottky diode placed in parallel with the body diode. The Schottky diode is forward biased by a voltage drop which is lower than the voltage drop needed to forward bias the body diode, and therefore the Schottky diode bypasses all current from the source of the DMOS transistor while preventing the body diode from becoming forward biased. The resultant structure increases the operational speed of the DMOS transistor by reducing the storage of minority carriers in the body diode. However, the DMOS structure of Cogan does not account for the effects of parasitic BJTs associated with a power DMOS structure on an integrated circuit having many other transistors on the same substrate.